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Fault Secure Encoder and Decoder For NanoMemory Applications
07-06-2012, 03:01 PM
Post: #1
Fault Secure Encoder and Decoder For NanoMemory Applications
Fault Secure Encoder and Decoder For NanoMemory Applications


.ppt  Fault Secure Encoder and Decoder.ppt (Size: 1.03 MB / Downloads: 18)

INTRODUCTION

The Encoder, Decoder and Memory circuits are the applications of the Nano memory and Nano PLA architecture.
Memory cells have been protected from soft errors for more than a decade.
Due to the increase in soft error rate in logic circuits, the encoder and decoder circuitry around the memory blocks have become susceptible to soft errors.
In this project, We introduce a fault-tolerant Nano scale memory architecture which tolerates transient faults both in the storage unit and in the supporting logic (i.e., encoder, decoder (corrector), and detector circuitries).
The error-correcting codes (ECCs) are used for the existence of a simple fault-tolerant detector design.
The ECC codeword has an appropriate redundancy structure such that it can detect errors occurring in both the stored codeword in memory and the surrounding circuitries. This type of error-correcting codes, fault-secure detector capable ECCs (FSD-ECC).

AIM OF THE PROJECT

Introducing a new approach to design fault-secure encoder and decoder circuitry for memory designs.
Identifying and defining a new class of error-correcting codes whose redundancy makes the design of fault-secure detectors (FSD) particularly simple.
Euclidean Geometry Low-Density Parity-Check (EG-LDPC) codes have the fault-secure detector capability.
Using EG-LDPC codes, we can tolerate bit or nanowire defect rates of 10% and fault rates of 10-18 upsets/device/cycle, achieving a FIT rate at or below one for the entire memory system and a memory density of 1011 bit/cm2 with nanowire pitch of 10 nm for memory blocks of 10 Mb or larger.

System Overview

Referring Figure, The information bits are fed into the encoder to encode the information vector, and the fault secure detector of the encoder verifies the validity of the encoded vector.
If the detector detects any error, the encoding operation must be redone to generate the correct codeword.
The codeword is then stored in the memory.
During memory access operation, the stored code words will be accessed from the memory unit.
Code words are susceptible to transient faults while they are stored in the memory; therefore a corrector unit is designed to correct potential errors in the retrieved code words.
In our design all the memory words pass through the corrector and any potential error in the memory words will be corrected. Similar to the encoder unit, a fault-secure detector monitors the operation of the corrector unit.

EUCLIDEAN GEOMETRY CODE

Euclidean Geometry codes are also called EG-LDPC codes based on the fact that they are low-density Parity-check (LDPC) codes.
LDPC codes have a limited number of 1’s in each row and column of the matrix; this limit guarantees limited complexity in their associated detectors and correctors making them fast and light weight.
Let EG be a Euclidean Geometry with n points and J lines.
EG is a finite geometry that is shown to have the following fundamental structural properties:
Every line consists of ρ points.
Any two points are connected by exactly one line;
Every point is intersected by γ lines;
Two lines intersect in exactly one point or they are parallel.

CONCLUSION

This project develops a fault-secure encoder unit using a concurrent parity prediction scheme.
Like the general parity-prediction technique, concurrently generates (predicts) the parity-bits of the encoder outputs (encoded bits) from the encoder inputs (information bits).
The predicted parity bits are then compared against the actual parity function of the encoder output (encoded bits) to check the correctness of the encoder unit.
The parity predictor circuit implementation is further optimized for each ECC to make a more compact design.
For this reason, efficient parity prediction designs are tailored to a specific code.
Simple parity prediction guarantees single error detection; however, no generalization is given for detecting multiple errors in the detector other than complete replication of the prediction and comparison units.
The system reliability, area and performance area are specifically important when designing the fault tolerant designs.


?
Q
18-03-2014, 03:21 AM
Post: #2
RE: Fault Secure Encoder and Decoder For NanoMemory Applications
i want neat ,clear and MORE EXPLANATION ABOUT EG LDPC CODES.
Q

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