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## Implementation of ScramblerDescrambler for use with SONETOTNPosted by: seminar class Created at: Tuesday 26th of April 2011 12:53:55 AM Last Edited Or Replied at :Tuesday 26th of April 2011 12:53:55 AM | vhdl scrambler x6 x6 1 ,
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self-synchronizing • Polynomial X7 + X6 + 1 • Scrambler is initialized with ones SONET..................[:=> Show Contents <=:] | |||

## Binary MultiplierPosted by: ajukrishnan Created at: Wednesday 09th of December 2009 06:00:49 AM Last Edited Or Replied at :Tuesday 26th of July 2011 11:09:23 PM | binary multiplier sequential,
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hich is independent of the number of bits of the two operands.Also implemented are combinations of
dadda-booth and wallace-booth Index Terms-Modified Booth Algorithm, Wallace tree, Dadda tree, Carry-save adder, Carry Look-Ahead adder................... [:=> Show Contents <=:] | |||

## Implementation of stepper motor control using VHDL on FPGAPosted by: electronics seminars Created at: Tuesday 01st of December 2009 07:05:35 AM Last Edited Or Replied at :Wednesday 27th of July 2011 11:06:06 PM | FPGA,
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TITLE : Implementation of stepper motor control using VHDL on FPGA.
DESCRIPTION: The main aim of project i.................. [:=> Show Contents <=:] | |||

## DUAL PORT FIFOPosted by: computer science crazy Created at: Thursday 17th of September 2009 11:26:23 AM Last Edited Or Replied at :Saturday 08th of September 2012 06:34:39 PM | DUAL PORT FIFO,
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PORT FIFO Abstract:- The dual port FIFO is now a standard building block in most designs, especially in the area of communications where it is used frequently for packet work. A.................. [:=> Show Contents <=:] | |||

## IMPLEMENTATION OF ADVANCED ENCRYPTION STANDARD AESPosted by: computer science crazy Created at: Wednesday 16th of September 2009 03:33:00 PM Last Edited Or Replied at :Wednesday 14th of March 2012 04:20:53 AM | STANDARD ,
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tes together forming 4-term polynomials and multiplies the polynomials with a fixed polynomial mod
(x^4+1). The fourth stage AddRoundKey transformation adds the round key with the block of data. The hardware implementation of AES could provide either high performance or low cost for specific applications. At backbone communication channels, or at heavily loaded server, it is not possible to lose processing speed running cryptography algorithms in general software, which drops the efficiency of the overall system. On the other side, a low cost and small design can be used in smart card ap.................. [:=> Show Contents <=:] | |||

## Multiplier Accumulator Component VHDL ImplementationPosted by: seminar projects crazy Created at: Friday 14th of August 2009 05:36:54 AM Last Edited Or Replied at :Thursday 23rd of February 2012 05:25:46 AM | Implementation,
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ensively used in Fast Fourier Transforms required by the MP3 Chip. The 16 bit multiplier accumulator
unit is based on the multiplier accumulator specification of the Analog Devices ADSP2181 chip. Field Programmable Gate Arrays (FPGAs) are being used increasingly in embedded general purpose computing environments as performance accelerators. This new use beyond the traditional usage as glue logic and as a rapid prototyping enabler has also renewed interest in the FPGA architecture. The fine grain reconfigurability of the FPGA architecture makes it an ideal candidate for use in system-on-chip.................. [:=> Show Contents <=:] | |||

## Design of Manchester Encoder-decoder in VHDLPosted by: seminar projects crazy Created at: Friday 14th of August 2009 05:30:15 AM Last Edited Or Replied at :Sunday 13th of November 2011 10:07:10 PM | VHDL,
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The language has been through a few revisions, and you will come across this in the VHDL community...................[:=> Show Contents <=:] | |||

## VHDL VHSIC Hardware Description LanguagePosted by: Computer Science Clay Created at: Thursday 30th of July 2009 05:46:09 AM Last Edited Or Replied at :Thursday 30th of July 2009 05:46:09 AM | Language ,
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nguage. It felt that there was a need to make the language industry standard. In 1985, the DOD
granted a permission to hand over the specs to IEEE. Subsequently IEEE released the IEEE 1076/A
standard in 1987. It was later revised in 1993. The 1993 revisions are minor and many of the
simulation and synthesis tools have not yet adopted them. It is an object-oriented language and
therefore people familiar with C++ or PASCAL can grasp it easily. VHDL can wear many hats. It is
being used for documentation, verification, and synthesis of large digital designs. This is actually
one of the key feature..................[:=> Show Contents <=:] |

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